Fundamentals of Layout Design for Electronic Circuits
Jens Lienig, Juergen Scheible
2020, 306 pages, Springer International Publishing
ISBN 978-3-030-39283-3, eBook ISBN 978-3-030-39284-0
DOI 10.1007/978-3-030-39284-0
简介
本书从基础出发，全面介绍了布局设计的基本知识，既包括数字电路中常见的物理设计，也涵盖了模拟布局。
这种知识为布局设计师提供了关键的认识和洞察力，使其能够将电路设计阶段生成的结构描述转化为用于 IC/PCB 制造的物理布局。
本书介绍了将硅转化为功能器件的技术知识，并深入探讨了布局所针对的技术（第2章）。
以核心技术知识为基础，后续章节将深入探讨物理设计的具体约束和方面，例如接口、设计规则和库（第3章）、设计流程和模型（第4章）、设计步骤（第5章), 模拟设计的具体内容（第6章），以及最后的可靠性措施（第7章）。除了作为工程学生的教科书外，这本书也是当今电路设计师的基础参考书。
目录
Foreword
Preface
Contents
1 Introduction
1.1 Electronics Technologies
1.1.1 Printed Circuit Board Technology
1.1.2 Hybrid Technology
1.1.3 Semiconductor Technology
1.2 Integrated Circuits
1.2.1 Importance and Characteristics
1.2.2 Analog, Digital and Mixed-Signal Circuits
1.2.3 Moore’s Law and Design Gaps
1.3 Physical Design
1.3.1 Main Design Steps
1.3.2 Physical Design of Integrated Circuits
1.3.3 Physical Design of Printed Circuit Boards
1.4 Motivation and Structure of This Book
References
2 Technology Know-How: From Silicon to Devices
2.1 Fundamentals of IC Fabrication
2.2 Base Material Silicon
2.3 Photolithography
2.3.1 Fundamentals
2.3.2 Photoresist
2.3.3 Photomasks and Exposure
2.3.4 Alignment and Alignment Marks
2.3.5 Reference to Physical Design
2.4 Imaging Errors
2.4.1 Overlay Errors
2.4.2 Edge Shifts
2.4.3 Diffraction Effects
2.4.4 Reference to Physical Design
2.5 Applying and Structuring Oxide Layers
2.5.1 Thermal Oxidation
2.5.2 Oxidation by Deposition
2.5.3 Oxide Structuring by Etching
2.5.4 Local Oxidation
2.5.5 Reference to Physical Design
2.6 Doping
2.6.1 Background
2.6.2 Diffusion
2.6.3 Ion Implantation
2.6.4 Reference to Physical Design
2.7 Growing and Structuring Silicon Layers
2.7.1 Homoepitaxy
2.7.2 Heteroepitaxy and Polysilicon
2.7.3 Reference to Physical Design
2.8 Metallization
2.8.1 Fundamentals
2.8.2 Metallization Structures Without Planarization
2.8.3 Metallization Structures with Planarization
2.8.4 Reference to Physical Design
2.9 CMOS Standard Process
2.9.1 Fundamentals: The Field-Effect Transistor
2.9.2 Process Options
2.9.3 FEOL: Creating Devices
2.9.4 BEOL: Connecting Devices
References
3 Bridges to Technology: Interfaces, Design Rules, and Libraries
3.1 Circuit Data: Schematics and Netlists
3.1.1 Structural Description of a Circuit
3.1.2 Idealizations in Circuit Descriptions
3.1.3 Circuit Representation: Netlist and Schematic
3.2 Layout Data: Layers and Polygons
3.2.1 Structure of Layout Data
3.2.2 How to Read a Layout View
3.2.3 Graphics Operations
3.3 Mask Data: Layout Post Processing
3.3.1 Overview
3.3.2 Chip Finishing
3.3.3 Reticle Layout
3.3.4 Layout-to-Mask Preparation
3.4 Geometrical Design Rules
3.4.1 Technological Constraints and Geometrical Design Rules
3.4.2 Basic Geometrical Design Rules
3.4.3 Programmed Geometrical Design Rules
3.4.4 Rules for Die Assembly
3.5 Libraries
3.5.1 Process Design Kits and Primitive Device Libraries
3.5.2 Cell Libraries
3.5.3 Libraries for Printed Circuit Board Design
References
4 Methodologies for Physical Design: Models, Styles, Tasks, and Flows
4.1 Design Flow
4.2 Design Models
4.2.1 Three-Dimensional Design Space
4.2.2 The Gajski-Kuhn Y-Chart
4.3 Design Styles
4.3.1 Full-Custom and Semi-Custom Design
4.3.2 Top-Down, Bottom-Up and Meet-in-the-Middle Design
4.4 Design Tasks and Tools
4.4.1 Creating: Synthesis
4.4.2 Checking: Analysis
4.4.3 Eliminating Deficiencies: Optimization
4.5 Physical Design Optimization and Constraints
4.5.1 Optimization Goals
4.5.2 Constraint Categories
4.5.3 Physical Design Optimization
4.6 Analog and Digital Design Flows
4.6.1 The Different Worlds of Analog and Digital Design
4.6.2 Analog Design Flow
4.6.3 Digital Design Flow
4.6.4 Mixed-Signal Design Flow
4.7 Visions for Analog Design Automation
4.7.1 A “Continuous” Layout Design Flow
4.7.2 A “Bottom-Up Meets Top-Down” Layout Design Flow
References
5 Steps in Physical Design: From Netlist Generation to Layout Post Processing
5.1 Generating a Netlist Using Hardware Description Languages
5.1.1 Overview and History
5.1.2 Elements and Example
5.1.3 Flow
5.2 Generating a Netlist Using Symbolic Design Entry
5.2.1 Overview
5.2.2 Elements and Examples
5.2.3 Netlist Generation
5.3 Primary Steps in Physical Design
5.3.1 Partitioning and Floorplanning
5.3.2 Placement
5.3.3 Routing
5.3.4 Physical Design Using Symbolic Compaction
5.3.5 Physical Design Using Standard Cells
5.3.6 Physical Design of Printed Circuit Boards
5.4 Verification
5.4.1 Fundamentals
5.4.2 Formal Verification
5.4.3 Functional Verification: Simulation
5.4.4 Timing Verification
5.4.5 Geometric Verification: DRC, ERC
5.4.6 Extraction and LVS
5.5 Layout Post Processing
References
6 Special Layout Techniques for Analog IC Design
6.1 Sheet Resistance: Calculating with Squares
6.2 Wells
6.2.1 Implementation
6.2.2 Breakdown Voltage
6.2.3 Voltage-Dependent Spacing Rules
6.3 Devices: Layout, Connection, and Sizing
6.3.1 Field-Effect Transistors (MOS-FETs)
6.3.2 Resistors
6.3.3 Capacitors
6.3.4 Bipolar Transistors
6.4 Cell Generator: From Parameters to Layout
6.4.1 Overview
6.4.2 Example
6.5 The Importance of Symmetry
6.5.1 Absolute and Relative Accuracy: The Big Difference
6.5.2 Obtaining Symmetry by Matching Devices
6.6 Layout Matching Concepts
6.6.1 Matching Concepts for Internal Device Fringe Effects
6.6.2 Matching Concepts for Unknown Gradients
6.6.3 Matching Concepts for External Device Fringe Effects
6.6.4 Matching Concepts for Known Gradients
6.6.5 Matching Concepts for Orientation-Dependent Effects
6.6.6 Summary of Matching Concepts
References
7 Addressing Reliability in Physical Design
7.1 Parasitic Effects in Silicon
7.1.1 Substrate Debiasing
7.1.2 Injection of Minority Carriers
7.1.3 Latchup
7.1.4 Breakdown Voltage, aka Blocking Capability, of p–n Junctions
7.2 Surface Effects
7.2.1 Parasitic Channel Effects
7.2.2 Hot Carrier Injection
7.3 Interconnect Parasitics
7.3.1 Line Losses
7.3.2 Signal Distortions
7.3.3 Crosstalk
7.4 Overvoltage Protection
7.4.1 Electrostatic Discharge (ESD)
7.4.2 Antenna Effect
7.5 Migration Effects in Metal
7.5.1 Electromigration
7.5.2 Thermal Migration
7.5.3 Stress Migration
7.5.4 Mitigating Electromigration
7.5.5 Mitigating Thermal and Stress Migration
References
Index